Semiconductor memory with alternately multiplexed row and column addressing

ABSTRACT

The semiconductor memory receives an external clock signal and has the memory cell array access operation controlled based on the clock signal. In the application of this semiconductor memory to a dynamic RAM, for example, a row address and column address are introduced in synchronism with the clock signal. The read, write and refresh operations are controlled based on the clock signal.

BACKGROUND OF THE INVENTION

This invention relates to a semiconductor memory, such as a dynamic RAM,for example.

Conventional semiconductor memories, such as dynamic RAMs, are based onthe input multiplexing of the row address and column address, and theynecessitate a row address strobe, column address strobe and severalother timing signals including write control signals, as is well knownin the art.

A computer system generally operates in synchronism with a constantsystem clock, and data to be read out or written into a storage unit istransferred also in synchronism with the system clock. Accordingly, fora storage unit based on the dynamic RAM, in which several timing signalsare produced from the system clock, these timing signals need to be setto meet the prescribed timings even in the worst condition inconsideration of the variability in the signal delay time, crosstalknoise, and the like. On this account, conventional semiconductormemories cannot fully exert their inherent performances.

SUMMARY OF THE INVENTION

An object of this invention is to provide a semiconductor memory, e.g.,a dynamic RAM, which operates with its full performance.

The inventive address-multiplexed semiconductor memory is designed toreceive a clock signal and a chip select signal from the outside andhave its memory cell array access controlled based on the clock signal.Consequently, by supplying an external clock signal which meets theperformance of the semiconductor memory, it can operate with its fullperformance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the semiconductor memory according to anembodiment of this invention;

FIGS. 2A and 2B are timing charts used to explain the operation of thearrangement shown in FIG. 1;

FIG. 3 is a diagram showing the control circuit and its periphery inFIG. 1; and

FIGS. 4, 5 and 6 are timing charts used to explain the operation of thearrangement shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A specific embodiment of this invention will be described with referenceto the drawings.

In FIG. 1, a system clock CLK, which is produced inside a computersystem, is supplied from the outside of the semiconductor memory, and itis delivered to the clock input terminals of latches 81-84 in a latchcircuit 8 and the clock input terminal of a control circuit 1. Alsosupplied from the outside are a chip select signal {overscore (CS)},write enable signal {overscore (WE)}, and write data DIN, that aredelivered to the latches 81-83 in the latch circuit 8 in synchronismwith the system clock CLK. The readout data DOUT from the latch 84 inthe latch circuit 8 is delivered to the outside.

The control circuit 1 produces a row address set signal RS1, which isdelivered to the set input terminal of a row latch 2, which thenintroduces a row address multiplexed in the address signals A0-A9.Similarly, the column address set signal CS1 is delivered to the setinput terminal of a column latch 4, which then introduces a columnaddress multiplexed in the address signals A0-A9. Thus, the controlcircuit 1 and latches 2,4 demultiplex the address signals A0-A9.

The row latch 2 has its output signals delivered to the input terminalsof a row decoder 3, which produces output signals X0-X1023 that areplaced on the row lines (not shown) of a memory cell array 7. The columnlatch 4 has its output signals delivered to the input terminals of acolumn decoder 5, which produces output signals that are applied to theinput terminals of a column selection circuit 6. The column selectioncircuit 6 responds to the output signal of the column decoder 5 toselect one of data input/output signals Y0-Y1023 of the memory cellarray 7, so that the output of the latch 83 is written into a cell inwrite mode or data is read out to the latch 84 in read mode.

The operation of the foregoing arrangement will be explained on thetiming charts of FIGS. 2A and 2B. FIG. 2A shows the read cycle and writecycle, and FIG. 2B shows reading and writing in the page mode cycle, andthe refresh cycle and page mode cycle .

Read Cycle

The chip select signal {overscore (CS)} is brought to a low level beforethe clock signal CLK first rises in its read cycle, and a row addressRXi is applied to the address terminals A0-A9. The row address setsignal RS1 is produced at the first rising edge of the clock CLK, andthe row address RXi is latched in the latch 2 shown in FIG. 1. The rowdecoder 3 decodes the row address RXi which is latched in the row latch2 thereby to activate a selected one of the row lines X0-X1023, and theread operation starts. Subsequently, a column address RYi is applied tothe address terminals A0-A9 before the second rise of the clock signalCLK of the READ cycle. Then, the column address set signal CS1 isproduced at the second rising edge of the clock signal CLK, and thecolumn address RYi is latched in the column register 4 shown in FIG. 1.The column decoder 5 decodes the column address RYi which is latched inthe column latch 4, and the column selection circuit 6 selects one ofdata read out to the data input/output signal lines Y0-Y1023.Subsequently, at the third rise of the clock signal CLK in the READcycle, the data which has been selected by the column selection circuit6 is latched in the latch 84 in the latch circuit 8, and it is deliveredas valid data at the terminal DOUT. The chip select signal {overscore(CS)} is brought to a high level before third rise of the the clocksignal CLK in the READ cycle, and the READ cycle operation for thememory cell array 7 completes at the fourth rise of the clock signalCLK.

Write Cycle

The operation until the rise of the first clock signal CLK is identicalto the read cycle, and the explanation is omitted. The write enablesignal {overscore (WE)} is made low before the second rise of the clocksignal CLK of the WRITE cycle, and write data is applied to the datainput terminals DIN. The column address WYi is latched at the secondrise of the clock signal CLK, and the write data at DIN terminal islatched in the latch 83 in the latch circuit 8. The write data istransferred to one of the data input/output signal lines Y0-Y1023selected with the column address WYi by the column selection circuit 6,and it is written to the row line selected with the row address WXi.

Refresh Cycle

As in the read or write cycle, a refresh address RFi is latched in therow latch in response to the clock signal CLK of the first cycle and therow decoder 3 decodes the refresh address RFi latched in the latch 2 toactivate a selected one of the row lines X0-X1023, and the refreshoperation starts. Subsequently, the chip select signal {overscore (CS)}is made high before the second clock signal CLK goes high. The chipselect signal {overscore (CS)} is disactivated when the second clocksignal CLK rises, causing the column latch 4, column decoder 5 andcolumn selection circuit 6 to quit operation, and the data input/outputoperation does not take place. The clock signal CLK of the third secondcycle is a dummy for making cycles consistent with the read and writecycle, and the refresh cycle completes by using clock signals CLK ofthree cycles.

Page Mode Cycle

The operations until the rise of the first and second rise of clocksignal CLK are identical to the read or write cycle, and the explanationis omitted. In the third and following rises, reading or writing takesplace in synchronism with the rising of the clock signal CLK for the rowaddress (RXi or WXi respectively) and a column address (RY_(K), RY_(L)or WY_(K), WY_(L) respectively), which is different from the columnaddress (RY_(j) or WY_(j)) entered in the first and second cycles. Thepage mode cycle continues until the chip select signal {overscore (CS)}goes high. The figure shows the case in which row address RXi and columnaddresses RY_(j) , WY_(K) and WY_(L) are given in the respective firstthrough fourth rises of the clock signal CLK.

FIG. 3 is a diagram showing the control circuit 1 and its periphery inFIG. 1. In the figure, the chip select signal {overscore (CS)} isapplied to the data input terminal of the latch 81 in the latch circuit.The clock CLK is connected to the edge trigger T of the latch 81 theedge trigger T of the latch 10 in the control circuit 1 input terminaland delay circuit 12, 13.

The output signal {overscore (CCS)} of the latch 81 is delivered to theinverter 11, which has an output CCS delivered to the data inputterminal of latch 10 and input terminals of the two-input AND gate 14and three-input AND gate 15. The delay circuit 12, 13 has its outputsignal CLK1 applied to the input terminal of the three-input AND gate15.

The latch 10 has its output signal CT applied to the inverting inputterminal of the two-input AND gate 14 and to the input terminals of thethree-input AND gate 15. The two-input AND gate 14 produces the rowaddress set signal RS1 and the three-input AND gate 15 produces thecolumn address set signal CS1.

The operation of the circuit arrangement shown in FIG. 3 will beexplained for its read (write) cycle, refresh cycle and page mode read(or write) cycle, for example, on the timing charts of FIGS. 4, 5 and 6.

In the read (or write) cycle of FIG. 4, the chip select signal{overscore (CS)} is made low before the clock signal CLK rises at t₁,and a low chip select signal {overscore (CS)} is latched in the latch 81at the rise of the clock signal CLK at t₁. At this time point t₁, theoutput signal {overscore (CCS)} of the latch 81 is high. Because of alow data input signal CCS of the latch 10, it latches the signal at thelow level. The output signal CT of the latch 10 stays low until the riseof the next clock signal CLK at t₂. Because of a low input signal CCS ofthe two-input AND gate 14, it produces a low output signal RS1 at t₁.

After the clock signal CLK has risen at t₁, the output signal {overscore(CCS)} of the latch 81 goes low. Consequently, the output signal CCS ofthe inverter 11 goes high, causing the two-input AND gate 14 to output alow inverted input signal CT, and with high input signal CCS the ANDgate 14 produces a high row address set signal RS1.

Next, when the clock signal CLK rises at t₂, the latch 10 has a highdata input signal CCS and it latches the high-level signal. After theclock signal CLK has risen at t₂, the output signal CT of the latch 10goes high. Because of inverting the high signal CT at the input of thetwo-input AND gate 14, it produces a low output signal RS1. As the inputsignals CCS and CT of

the three-input AND gate 15 are high shortly after t₂, a clock signalCLK1 which is a delayed derivative of the clock signal CLK has itshigh-level portion between t₂ and t₃ delivered as a column address setsignal CS1.

Through the foregoing operation, it becomes possible to introduce a rowaddress and column address in the address signal A0-A9 to the row latch2 and column latch 4 sequentially.

Next, by making the chip select signal {overscore (CS)} high before theclock signal CLK rises at t₃, a high-level signal is latched in thelatch 81 at the rise of the clock signal CLK. After the clock signal CLKhas risen at t₃, the output signal {overscore (CCS)} of the latch 81goes high. Accordingly, the signal CCS goes low, and the column addressset signal CS1 produced by the three-input AND gate 15 goes low andstays low until the next rise of the clock signal CLK and lowering ofthe chip select signal CS.

Next, when the clock signal CLK rises at t₄, the signal CCS is low andthe latch 10 latches the low-level signal to lower its output CT. Afterthe clock signal CLK has risen at t₄, the output signal {overscore(CCS)} of the latch 81 goes low. Because of a low output signal CT ofthe latch 10, the two-input AND gate 14 produces a high row address setsignal RS1 in response to the rise of its other input signal CCS.

The t₁ cycle and t₄ cycle have the same operation as described above,and it becomes possible to run the read (or write) cycles repeatedly.

FIG. 5 shows the refresh cycle. The cycle of t₁ is identical to that oft₁ of the read (or write) cycle, and explanation thereof is omitted.Since the refresh cycle does not need the column address, the chipselect signal {overscore (CS)} is made high before the clock signal CLKrises at t₂ so as to retain the high input signal {overscore (CS)} tothe latch 81. After the clock signal CLK has risen at t₂, output signal{overscore (CCS)} of the latch 81 goes high, causing the inverter 11 tohave a low inverting output signal CCS. Consequently, the low inputsignal CCS to the three-output AND gate 15 causes it to produce a columnaddress set signal CS1 at a low level.

In the cycle of t₃, the input signal CCS common to the two-input ANDgate 14 and three-input AND gate 15 is low, and therefore the rowaddress set signal RS1 and column address set signal CS1 are low. Theoperation of the t₄ cycle is identical to that of t₁ in FIG. 4 andexplanation thereof is omitted.

In this manner, a row address in the address signal A0-A9 is introducedto the row latch 2 and no column address is introduced for the refreshcycle.

FIG. 6 shows the page mode read (or write) cycle. The cycle of t₁operates identically to that of t₁ in FIG. 4, in which a row address inthe address signal A0-A9 is introduced to the row latch 2. The cycle oft₂₁ operates identically to that of t₂ in FIG. 4, in which a columnaddress in the address signal A0-A9 is introduced to the column latch 4.

In the cycle of t₂₂, a column address in the address signal A0-A9 isintroduced again to column latch 4, as in the t₂₁ cycle. Namely, onlycolumn addresses are introduced successively. The cycle of t₃ isidentical to that of t₃ in FIG. 4 and the explanation thereof isomitted.

In this manner, for the page mode read (or write) cycle, a row addressin the address signal A0-A9 is introduced to the row latch 2, andthereafter column addresses in the address signal A0-A9 are introducedsuccessively to the column latch 4.

According to the foregoing embodiment, a semiconductor memory which isbased on address multiplexing and is operative on a single clock signalcan be accomplished by merely adding a few latch circuits and associatedcontrol circuit to the conventional MOS dynamic RAM.

Although the foregoing embodiment is the case of writing and reading forone-bit data, this invention is not confined to this case, but thearrangement for dealing with multiple-bit data can also be accomplished.Although in the foregoing embodiment an external row address isintroduced for the refresh address, it is also possible to provide aninternal address counter, thereby eliminating the need of the externaladdress input.

We claim:
 1. A semiconductor memory chip, comprising: a memory cellarray; means of receiving an address signal having a row address signaland a column address signal in such a manner that the row address signalis received first and then the column address signal is subsequentlyreceived; means of communication with the outside for inputting andoutputting data to and from said memory cell array; means for receivinga clock signal having a series of clock pulses; means for receiving achip select signal from the outside which represents that thesemiconductor memory is selected; means responsive to the clock signaland the chip select signal for generating a row address set signal and acolumn address set signal, wherein the row address set signal isgenerated under a circumstance where the semiconductor memory receives afirstly occurred clock pulse of the series of the clock pulses of theclock signal while the chip select signal is being provided to thesemiconductor memory, and wherein the column address set signal isgenerated under a circumstance where the semiconductor memory receives asubsequent clock pulse while the chip select signal is being provided tothe semiconductor memory; means responsive to the row address set signalfor setting the address signal from the means of receiving as the rowaddress signal and for providing the memory cell array with the set rowaddress signal; and means responsive to the column address set signalfor setting the address signal from the means of receiving as the columnaddress signal and for providing the memory cell array with the setcolumn address signal.
 2. A semiconductor memory according to claim 1,wherein said memory cell array is of the dynamic type which requires arefresh operation, and wherein said control means controls the refreshoperating further including means for conducting the refresh operationbased on said clock signal.
 3. A semiconductor memory according to claim1 operable with a page mode, wherein the means for generating furthergenerates a continuous series of column address set signals insynchronism with said clock signal as long as the chip select signal isprovided, whereby memory access to a plurality of memory cells belongingto the same row is continuously performed in accordance with the seriesof the column address set signals.
 4. A semiconductor RAM chip,comprising: an address input terminal for receiving an address signalhaving row and column addresses time multiplexed; a chip select inputterminal for receiving a chip select signal to indicate the selection ofthe semiconductor RAM; a clock input terminal for receiving a clockhaving a single periodic succession of clock pulses; a memory cellarray; a data output terminal connected to said memory cell array tooutput data from said memory cell; a data input terminal connected tosaid memory cell array for receiving data for said memory cell; a rowaddress decoder having a row address input and an output connected tosaid memory cell array; a column address decoder having a column addressinput and an output connected to said memory cell array; and means forreceiving the multiplexed address signal from said address inputterminal and the clock from said clock input terminal, and foroutputting the row address to the input of the row address decoderseparate from the column address and outputting the column address tothe input of the column address decoder separate from the row address inresponse to only the clock when the chip select signal at said chipselect input terminal indicates the selection of the semiconductor RAM.5. The semiconductor RAM of claim 4, further comprising: a columnselection circuit operatively connected between said memory cell arrayand each of said data output terminal, data input terminal and means forreceiving and outputting; an enable input terminal for receiving anenable signal to indicate a selection of one of a write operation and aread operation; said column selection circuit including means responsiveto said enable signal for controlling the data connection between saidmemory cell array and each of said data input terminal and data outputterminal; a latch operatively connected between said data outputterminal and said column selection circuit for the transfer of data andoperatively connected to said clock input terminal for controlling thetransferred timing; a latch operatively connected between said datainput terminal and said column selection circuit for the transfer ofdata and operatively connected to said clock input terminal forcontrolling the transferred timing; latch means operatively connectedbetween said chip select input terminal and said means for receiving andoutputting, and connected to receive the clock from said clock inputterminal; latch means operatively connected between said enable inputterminal and said column selection circuit, and connected to receive theclock form from said clock input terminal; said means for receiving andoutputting including a control circuit connected to said clock inputterminal for receiving the clock, connected to said chip select inputterminal for receiving the chip select signal through the correspondinglatch means, outputting a row address set signal, and outputting acolumn address set signal; said means for receiving and outputtingfurther including row latch means operatively connected to said addressinput terminal for receiving the multiplexed address signal andoutputting only the row address signal in response to the row addressset signal form from the control circuit to said row address decoder,and said means for receiving and outputting further including columnlatch means operatively connected to said address input terminal forreceiving the multiplexed address signal and outputting only the columnaddress signal in response to the column address set signal from thecontrol circuit to said column address decoder.
 6. The semiconductor RAMof claim 5, wherein said control circuit means for receiving andoutputting consists of latch and logic elements.
 7. The semiconductorRAM of claim 6, wherein said control circuit means for receiving andoutputting includes delay means for producing a delayed clock from theclock, first AND-gate means inputting the clock and a chip select signaland outputting the row address et set signal, second AND-gate meansinputting the chip select signal and the clock for outputting the columnaddress set signal.
 8. The semiconductor RAM of claim 7, wherein saidfirst and second AND-gate means are operative on the opposite sign logicof the clock with respect to each other.
 9. The semiconductor RAM ofclaim 7, wherein said control circuit means for receiving and outputtingfurther includes a latch operative to feed the chip select signal toonly one of said first and second AND-gate means synchronized with theclock, and the other of said first and second AND-gate means receivingthe chip select signal bypassing the latch.
 10. The semiconductor RAM ofclaim 4, wherein said means for receiving and operating outputtingproduces a row address set signal from only the clock and the chipselect signal and further produces a column address set signal from onlythe clock and the chip select signal; and first means for separating therow address from the multiplexed address signal and feeding theseparated row address to said row address decoder in response to onlythe row address set signal, and second means for separating the columnaddress from the multiplexed address signal and feeding the separatedcolumn address to said column address decoder in response to only thecolumn address set signal.
 11. The semiconductor RAM of claim 10 ,wherein said control circuit means for receiving and outputting isresponsive to the first operative pule pulse of the clock when the chipselect signal indicates selection of the semiconductor RAM foroutputting the row address set signal.
 12. The semiconductor RAM ofclaim 11, wherein said control circuit means for receiving andoutputting is responsive to the second operative pulse of the clock whenthe chip select signal indicates selection of the semiconductor RAM foroutputting the column address set signal.
 13. The semiconductor RAM ofclaim 12, wherein said control circuit means for receiving andoutputting is responsive to the third operative pulse of the clock whenthe chip select signal indicates selection of the semiconductor RAM foragain outputting the column address set signal to provide a page mode bymerely extending the duration of the chip select signal.
 14. Thesemiconductor RAM of claim 13, wherein said control circuit means forreceiving and outputting determines the operative pulse of the clock asan edge of each successive pulse of the clock.
 15. A semiconductormemory chip, comprising: an address input terminal for receiving anaddress signal having row and column addresses time multiplexed; aninput terminal for receiving a control signal that is selectivelyactive; a clock input terminal for receiving a clock having a singleperiodic succession of clock pulses; a memory cell array; a data outputterminal connected to said memory cell array to output data from saidmemory cell array; a row address decoder having a row address input andan output connected to said memory cell array; a column address decoderhaving a column address input and an output connected to said memorycell array; and demultiplexing means for receiving the multiplexedaddress signal from said address input terminal and the clock from saidclock input terminal, and for outputting the row address to the input ofthe row address decoder separate from the column address and outputtingthe column address to the input of the column address decoder separatefrom the row address in response to only the timing of the clock whenthe control signal at said input terminal is active.
 16. Thesemiconductor memory of claim 15, further comprising: a data inputterminal connected to said memory cell array for receiving data for saidmemory cell; a column selection circuit operatively connected betweensaid memory cell array and each of said data output terminal, data inputterminal and demultiplexing means for receiving and outputting; anenable input terminal for receiving an enable signal to indicate aselection of one of a write operation and a read operation; said columnselection circuit including means responsive to said enable signal forcontrolling the data connection between said memory cell array and eachof said data input terminal and data output terminal; a latchoperatively connected between said data output terminal and said columnselection circuit for the transfer of data and operatively connected tosaid clock input terminal for controlling the transferred timing; alatch operatively connected between said data input terminal and saidcolumn selection circuit for the transfer of data and operativelyconnected to said clock input terminal for controlling the transferredtiming; latch means operatively connected between said input terminal ofthe control signal and said demultiplexing means for receiving andoutputting, and connected to receive the clock from said clock inputterminal; latch means operatively connected between said enable ableinput terminal and said column selection circuit, and connected toreceive the clock from said clock input terminal; said demultiplexingmeans for receiving and outputting including a control circuit connectedto said clock input terminal for receiving the clock, connected to saidinput terminal for receiving the control signal through thecorresponding latch means, outputting a row address set signal, andoutputting a column address set signal; said demultiplexing means forreceiving and outputting further including row latch means operativelyconnected to said address input terminal for receiving the multiplexedaddress signal and outputting only the row address signal in response tothe row address set signal from the control circuit to said row addressdecoder, and said demultiplexing means for receiving and outputtingfurther including column latch means operatively connected to saidaddress input terminal for receiving the multiplexed address signal andoutputting only the column address signal in response to the columnaddress set signal from the control circuit to said column addressdecoder.
 17. The semiconductor memory of claim 16, wherein said controlcircuit consists of latch and logic elements.
 18. The semiconductormemory of claim 17, wherein said control circuit includes delay meansfor producing a delayed clock from the clock, first AND-gate meansinputting the clock and a chip select signal and outputting the rowaddress set signal, second AND-gate means inputting the chip selectsignal and the clock for outputting the column address set signal. 19.The semiconductor memory of claim 18, wherein said first and secondAND-gate means are operative on the opposite sign logic of the clockwith respect to each other.
 20. The semiconductor memory of claim 17,wherein said control circuit further includes a latch operative to feedthe control signal to only one of said first and second AND-gate meanssynchronized with the clock, and the other of said first and secondAND-gate means receiving the control signal bypassing the latch.
 21. Thesemiconductor memory of claim 15, wherein said demultiplexing means forreceiving and operating outputting produces a row address set signalfrom only the clock and the control signal and further produces a columnaddress set signal from only the clock and the control signal; and firstmeans for separating the row address from the multiplexed address signaland feeding the separated row address to said row address decoder inresponse to only the row address set signal, and second means forseparating the column address from the multiplexed address signal andfeeding the separated column address to said column address decoder inresponse to only the column address set signal.
 22. The semiconductormemory of claim 21, wherein said control circuit is responsive to thefirst operative pule pulse of the clock when the control signal isactive for outputting the row address set signal.
 23. The semiconductormemory of claim 22, wherein said control circuit is responsive to thesecond operative pulse of the clock when the control signal is activefor outputting the column address set signal.
 24. The semiconductormemory of claim 23, wherein said control circuit is responsive to thethird operative pulse of the clock when the control signal is active foragain outputting the column address set signal to provide a page mode bymerely extending the duration of the chip select signal.
 25. Thesemiconductor memory of claim 24, wherein said control circuitdetermines the operative pulse of the clock as an edge of eachsuccessive pulse of the clock.
 26. A semiconductor dynamic memory chip,comprising: a dynamic type random access memory cell array: an addressinput terminal to be supplied with address signals having timemultiplexed row address signals and column address signals; a rowaddress latch having an input which is supplied with said row addresssignals from said address input terminal; a column address latch havingan input which is supplied with said column address signals from saidaddress input terminal; a first latch circuit having an input which issupplied with an external chip select signal and a latch timing controlterminal which is supplied with an external clock signal having acontinuous succession of clock pulses of constant period; a second latchcircuit having an input which is supplied with a write enable signal anda latch timing control terminal which is supplied with said externalclock signal; a data input latch circuit having a data input which issupplied with an external data, a latch timing control terminal which issupplied with said external clock signal and a data output terminalwhich is coupled with said dynamic type random access memory cell array;a data output latch circuit having a data input which is coupled withsaid dynamic type random access memory cell array, an output timingcontrol terminal which is supplied with said external clock signal and adata output terminal; a row address decoder having an input which iscoupled with an output of said row address latch and an output which iscoupled with said dynamic type random access memory cell array; and acolumn address decoder having an input which is coupled with an outputof said column address latch and an output which is coupled with saiddynamic type random access memory cell array, wherein said row addresslatch latches said row address signals in response to said external chipselect signal latched by said first latch circuit and to a first levelchange of said external clock signal, and wherein said column addresslatch latches said column address signals in response to said externalchip select signal latched by said first latch circuit and to a secondlevel change which appears after said first level change of saidexternal clock signal.
 27. A semiconductor dynamic memory chip accordingto claim 26, wherein said data input latch circuit latches an input datain synchronism with said second level change.
 28. A semiconductordynamic memory chip according to claim 26, wherein said data outputlatch circuit outputs an output data in synchronism with a third levelchange which appears after said second level change of said externalwhich appears after said second level change of said external clocksignal.
 29. A semiconductor dynamic memory chip according to claim 26,wherein said data input latch circuit latches an input data insynchronism with said second level change, and wherein said data outputlatch circuit outputs an output data in synchronism with a third levelchange which appears after said second level change of said externalclock signal.
 30. A semiconductor dynamic memory chip according to claim29, wherein said column address latch latches a column address inresponse to the third level change of said external clock signal atwhich said data output latch circuit outputs the output data.
 31. Asemiconductor dynamic memory chip according to claim 29, wherein saidcolumn address latch latches repeatedly column address signals inresponse to each of a plurality of level changes which appear after saidfirst level change of said external clock signal under a state that saidrow address latch latches said row address signals in response to saidfirst level change.
 32. A semiconductor dynamic memory chip according toclaim 31, wherein said column address latch latches a column address inresponse to the third level change of said external clock signal atwhich said data output latch circuit outputs an output data.
 33. Asemiconductor dynamic memory chip according to claim 26, wherein saidexternal chip select signal has a predetermined low level, and whereinsaid first level change and said second level change go from a low levelto a high level.